﻿/*****************************************************************************
* vim:sw=8:ts=8:si:et
*
* Title        : Microchip ENC28J60 Ethernet Interface Driver
* Author        : Pascal Stang (c)2005
* Modified by Guido Socher and Guenther Hoelzl
* Ported to C# and modified for NETMF by hanzibal in 2011 with permission from
* Guenther Hoelzl
* Copyright: GPL V2
*
*This driver provides initialization and transmit/receive
*functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.
*This chip is novel in that it is a full MAC+PHY interface all in a 28-pin
*chip, using an SPI interface to the host processor.
*
*
*****************************************************************************/
/*********************************************
 * Modified: nuelectronics.com -- Ethershield for Arduino
 *********************************************/
//@{

namespace ENC68J60
{
    public partial class ENC68J60uIPDriver
    {
        // ENC28J60 Control Registers
        // Control register definitions are a combination of address,
        // bank number, and Ethernet/MAC/PHY indicator bits.
        // - Register address        (bits 0-4)
        // - Bank number        (bits 5-6)
        // - MAC/PHY indicator        (bit 7)
        const byte ADDR_MASK        = 0x1F;
        const byte BANK_MASK        = 0x60;
        const byte SPRD_MASK        = 0x80;
        // All-bank registers
        const byte EIE              = 0x1B;
        const byte EIR              = 0x1C;
        const byte ESTAT            = 0x1D;
        const byte ECON2            = 0x1E;
        const byte ECON1            = 0x1F;
        // Bank 0 registers
        const byte ERDPTL           = (0x00|0x00);
        const byte ERDPTH           = (0x01|0x00);
        const byte EWRPTL           = (0x02|0x00);
        const byte EWRPTH           = (0x03|0x00);
        const byte ETXSTL           = (0x04|0x00);
        const byte ETXSTH           = (0x05|0x00);
        const byte ETXNDL           = (0x06|0x00);
        const byte ETXNDH           = (0x07|0x00);
        const byte ERXSTL           = (0x08|0x00);
        const byte ERXSTH           = (0x09|0x00);
        const byte ERXNDL           = (0x0A|0x00);
        const byte ERXNDH           = (0x0B|0x00);
        const byte ERXRDPTL         = (0x0C|0x00);
        const byte ERXRDPTH         = (0x0D|0x00);
        const byte ERXWRPTL         = (0x0E|0x00);
        const byte ERXWRPTH         = (0x0F|0x00);
        const byte EDMASTL          = (0x10|0x00);
        const byte EDMASTH          = (0x11|0x00);
        const byte EDMANDL          = (0x12|0x00);
        const byte EDMANDH          = (0x13|0x00);
        const byte EDMADSTL         = (0x14|0x00);
        const byte EDMADSTH         = (0x15|0x00);
        const byte EDMACSL          = (0x16|0x00);
        const byte EDMACSH          = (0x17|0x00);
        // Bank 1 registers
        const byte EHT0             = (0x00|0x20);
        const byte EHT1             = (0x01|0x20);
        const byte EHT2             = (0x02|0x20);
        const byte EHT3             = (0x03|0x20);
        const byte EHT4             = (0x04|0x20);
        const byte EHT5             = (0x05|0x20);
        const byte EHT6             = (0x06|0x20);
        const byte EHT7             = (0x07|0x20);
        const byte EPMM0            = (0x08|0x20);
        const byte EPMM1            = (0x09|0x20);
        const byte EPMM2            = (0x0A|0x20);
        const byte EPMM3            = (0x0B|0x20);
        const byte EPMM4            = (0x0C|0x20);
        const byte EPMM5            = (0x0D|0x20);
        const byte EPMM6            = (0x0E|0x20);
        const byte EPMM7            = (0x0F|0x20);
        const byte EPMCSL           = (0x10|0x20);
        const byte EPMCSH           = (0x11|0x20);
        const byte EPMOL            = (0x14|0x20);
        const byte EPMOH            = (0x15|0x20);
        const byte EWOLIE           = (0x16|0x20);
        const byte EWOLIR           = (0x17|0x20);
        const byte ERXFCON          = (0x18|0x20);
        const byte EPKTCNT          = (0x19|0x20);
        // Bank 2 registers
        const byte MACON1           = (0x00|0x40|0x80);
        const byte MACON2           = (0x01|0x40|0x80);
        const byte MACON3           = (0x02|0x40|0x80);
        const byte MACON4           = (0x03|0x40|0x80);
        const byte MABBIPG          = (0x04|0x40|0x80);
        const byte MAIPGL           = (0x06|0x40|0x80);
        const byte MAIPGH           = (0x07|0x40|0x80);
        const byte MACLCON1         = (0x08|0x40|0x80);
        const byte MACLCON2         = (0x09|0x40|0x80);
        const byte MAMXFLL          = (0x0A|0x40|0x80);
        const byte MAMXFLH          = (0x0B|0x40|0x80);
        const byte MAPHSUP          = (0x0D|0x40|0x80);
        const byte MICON            = (0x11|0x40|0x80);
        const byte MICMD            = (0x12|0x40|0x80);
        const byte MIREGADR         = (0x14|0x40|0x80);
        const byte MIWRL            = (0x16|0x40|0x80);
        const byte MIWRH            = (0x17|0x40|0x80);
        const byte MIRDL            = (0x18|0x40|0x80);
        const byte MIRDH            = (0x19|0x40|0x80);
        // Bank 3 registers
        const byte MAADR1           = (0x00|0x60|0x80);
        const byte MAADR0           = (0x01|0x60|0x80);
        const byte MAADR3           = (0x02|0x60|0x80);
        const byte MAADR2           = (0x03|0x60|0x80);
        const byte MAADR5           = (0x04|0x60|0x80);
        const byte MAADR4           = (0x05|0x60|0x80);
        const byte EBSTSD           = (0x06|0x60);
        const byte EBSTCON          = (0x07|0x60);
        const byte EBSTCSL          = (0x08|0x60);
        const byte EBSTCSH          = (0x09|0x60);
        const byte MISTAT           = (0x0A|0x60|0x80);
        const byte EREVID           = (0x12|0x60);
        const byte ECOCON           = (0x15|0x60);
        const byte EFLOCON          = (0x17|0x60);
        const byte EPAUSL           = (0x18|0x60);
        const byte EPAUSH           = (0x19|0x60);
        // PHY registers
        const byte PHCON1           = 0x00;
        const byte PHSTAT1          = 0x01;
        const byte PHHID1           = 0x02;
        const byte PHHID2           = 0x03;
        const byte PHCON2           = 0x10;
        const byte PHSTAT2          = 0x11;
        const byte PHIE             = 0x12;
        const byte PHIR             = 0x13;
        const byte PHLCON           = 0x14;

        // ENC28J60 ERXFCON Register Bit Definitions
        const byte ERXFCON_UCEN     = 0x80;
        const byte ERXFCON_ANDOR    = 0x40;
        const byte ERXFCON_CRCEN    = 0x20;
        const byte ERXFCON_PMEN     = 0x10;
        const byte ERXFCON_MPEN     = 0x08;
        const byte ERXFCON_HTEN     = 0x04;
        const byte ERXFCON_MCEN     = 0x02;
        const byte ERXFCON_BCEN     = 0x01;
        // ENC28J60 EIE Register Bit Definitions
        const byte EIE_INTIE        = 0x80;
        const byte EIE_PKTIE        = 0x40;
        const byte EIE_DMAIE        = 0x20;
        const byte EIE_LINKIE       = 0x10;
        const byte EIE_TXIE         = 0x08;
        const byte EIE_WOLIE        = 0x04;
        const byte EIE_TXERIE       = 0x02;
        const byte EIE_RXERIE       = 0x01;
        // ENC28J60 EIR Register Bit Definitions
        const byte EIR_PKTIF        = 0x40;
        const byte EIR_DMAIF        = 0x20;
        const byte EIR_LINKIF       = 0x10;
        const byte EIR_TXIF         = 0x08;
        const byte EIR_WOLIF        = 0x04;
        const byte EIR_TXERIF       = 0x02;
        const byte EIR_RXERIF       = 0x01;
        // ENC28J60 ESTAT Register Bit Definitions
        const byte ESTAT_INT        = 0x80;
        const byte ESTAT_LATECOL    = 0x10;
        const byte ESTAT_RXBUSY     = 0x04;
        const byte ESTAT_TXABRT     = 0x02;
        const byte ESTAT_CLKRDY     = 0x01;
        // ENC28J60 ECON2 Register Bit Definitions
        const byte ECON2_AUTOINC    = 0x80;
        const byte ECON2_PKTDEC     = 0x40;
        const byte ECON2_PWRSV      = 0x20;
        const byte ECON2_VRPS       = 0x08;
        // ENC28J60 ECON1 Register Bit Definitions
        const byte ECON1_TXRST      = 0x80;
        const byte ECON1_RXRST      = 0x40;
        const byte ECON1_DMAST      = 0x20;
        const byte ECON1_CSUMEN     = 0x10;
        const byte ECON1_TXRTS      = 0x08;
        const byte ECON1_RXEN       = 0x04;
        const byte ECON1_BSEL1      = 0x02;
        const byte ECON1_BSEL0      = 0x01;
        // ENC28J60 MACON1 Register Bit Definitions
        const byte MACON1_LOOPBK    = 0x10;
        const byte MACON1_TXPAUS    = 0x08;
        const byte MACON1_RXPAUS    = 0x04;
        const byte MACON1_PASSALL   = 0x02;
        const byte MACON1_MARXEN    = 0x01;
        // ENC28J60 MACON2 Register Bit Definitions
        const byte MACON2_MARST     = 0x80;
        const byte MACON2_RNDRST    = 0x40;
        const byte MACON2_MARXRST   = 0x08;
        const byte MACON2_RFUNRST   = 0x04;
        const byte MACON2_MATXRST   = 0x02;
        const byte MACON2_TFUNRST   = 0x01;
        // ENC28J60 MACON3 Register Bit Definitions
        const byte MACON3_PADCFG2   = 0x80;
        const byte MACON3_PADCFG1   = 0x40;
        const byte MACON3_PADCFG0   = 0x20;
        const byte MACON3_TXCRCEN   = 0x10;
        const byte MACON3_PHDRLEN   = 0x08;
        const byte MACON3_HFRMLEN   = 0x04;
        const byte MACON3_FRMLNEN   = 0x02;
        const byte MACON3_FULDPX    = 0x01;
        // ENC28J60 MICMD Register Bit Definitions
        const byte MICMD_MIISCAN    = 0x02;
        const byte MICMD_MIIRD      = 0x01;
        // ENC28J60 MISTAT Register Bit Definitions
        const byte MISTAT_NVALID    = 0x04;
        const byte MISTAT_SCAN      = 0x02;
        const byte MISTAT_BUSY      = 0x01;
        // ENC28J60 PHY PHCON1 Register Bit Definitions
        const ushort PHCON1_PRST    = 0x8000;
        const ushort PHCON1_PLOOPBK = 0x4000;
        const ushort PHCON1_PPWRSV  = 0x0800;
        const ushort PHCON1_PDPXMD  = 0x0100;
        // ENC28J60 PHY PHSTAT1 Register Bit Definitions
        const ushort PHSTAT1_PFDPX  = 0x1000;
        const ushort PHSTAT1_PHDPX  = 0x0800;
        const ushort PHSTAT1_LLSTAT = 0x0004;
        const ushort PHSTAT1_JBSTAT = 0x0002;
        // ENC28J60 PHY PHSTAT2 Register Bit Definitions
        const ushort PHSTAT2_PFDPX  = 0x4000;
        const ushort PHSTAT2_TXSTAT = 0x2000;
        const ushort PHSTAT2_RXSTAT = 0x1000;
        const ushort PHSTAT2_COLSTAT= 0x0800;
        const ushort PHSTAT2_LSTAT  = 0x0400;
        const ushort PHSTAT2_DPXSTAT= 0x0200;
        const ushort PHSTAT2_PLRITY = 0x0020;

        // ENC28J60 PHY PHCON2 Register Bit Definitions
        const ushort PHCON2_FRCLINK = 0x4000;
        const ushort PHCON2_TXDIS   = 0x2000;
        const ushort PHCON2_JABBER  = 0x0400;
        const ushort PHCON2_HDLDIS  = 0x0100;

        // ENC28J60 Packet Control Byte Bit Definitions
        const byte PKTCTRL_PHUGEEN  = 0x08;
        const byte PKTCTRL_PPADEN   = 0x04;
        const byte PKTCTRL_PCRCEN   = 0x02;
        const byte PKTCTRL_POVERRIDE = 0x01;

        // SPI operation codes
        const byte ENC28J60_READ_CTRL_REG       = 0x00;
        const byte ENC28J60_READ_BUF_MEM        = 0x3A;
        const byte ENC28J60_WRITE_CTRL_REG      = 0x40;
        const byte ENC28J60_WRITE_BUF_MEM       = 0x7A;
        const byte ENC28J60_BIT_FIELD_SET       = 0x80;
        const byte ENC28J60_BIT_FIELD_CLR       = 0xA0;
        const byte ENC28J60_SOFT_RESET          = 0xFF;


        // The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
        // buffer boundaries applied to internal 8K ram
        // the entire available packet buffer space is allocated
        //
        // start with recbuf at 0/
        const ushort RXSTART_INIT   = 0x0000;
        // receive buffer end
        const ushort RXSTOP_INIT    = (0x1FFF - 0x0600 - 1);
        // ushort TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
        const ushort TXSTART_INIT   = (0x1FFF - 0x0600);
        // stp TX buffer at end of mem
        const ushort TXSTOP_INIT    = 0x1FFF;
        //
        // max frame length which the conroller will accept:
        const ushort MAX_FRAMELEN   = 1500;        // (note: maximum ethernet frame length would be 1518)
        //const byte MAX_FRAMELEN     600
    }
}